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true digital pwm controller (single - phase, single - rail) zspm1025c / zspm1025d datasheet ? 2016 integrated device technology, inc. 1 january 22, 2016 brief description the zspm1025c and zspm1025d are true - digital single - phase pwm controllers optimally configured for use with the murata power solutions 25a power block oklp - x/25 in smart digital power solutions. the zspm1025c and zspm1025d integrate a digital control loop, opti mized for maximum flexibility and stability as well as load step and steady - state performance. in addition, a rich set of protection functions is provided. t o simplify the system design, a set of optimized configuration options have been pre - prog rammed in the devices. these configurations can be selected by setting the values of two external resistors. reference solutions are available complete with lay out re commendations, example circuit board layouts, complete bill of materials and more. features ? application - optimized digital control loop ? advanced, digital control techniques ? tru - sample technology ? ? state - law control ? (slc) ? sub - cycle response ? (scr) ? improved t ransient response and noise immunity ? protection features ? over - current protection ? over - voltage protection (vin, vout) ? under - voltage protection (vin, vout) ? overloaded startup ? continuous retry (?hiccup?) mode for fault conditions ? pre - programmed for optimized use with murata power solutions 25a power block oklp - x/25 ? 2 - pin configuration for loop compensation, output voltage, and slew rate. ? operation from a single 5v or 3.3v supply benefits ? fast time - to - market using off - the - shelf, optimally configured controller and power block ? fast configuration and design flexibility ? simplified design and integration ? fpga designer - friendly solution ? highest power density with smallest footprint ? pin - to - pin compatible with the zspm1025a pwm controller enabling point - of - load platfo rm designs with or without digital communication ? higher energy efficiency across all output loading conditions available support ? evaluation kit ? reference solutions ? pc - based pink power designer? graphic user interface (gui) physical characteristics ? operatio n temperature: - 40c to +125c ? zspm1025c v out : 0.62v to 1.20v ? zspm1025d v out : 1.25v to 3.40v ? lead free (rohs compliant) 24- pin qfn p ackage (4mm x 4mm) zspm1025c/d typical application diagram driver zspm 1025 qfn 4 x4 mm murata oklp-x/25 -w 12-c current sensing digital control loop power management ( sequencing , protection , ?) housekeeping and communication driver
true digital pwm controller (single - phase, single - rail) zspm1025c / zspm1025d datasheet ? 2016 integrated device technology, inc. 2 january 22, 2016 typical applications ? telecom switches ? servers and storage ? base stations ? network routers ? industrial applications ? fpga designs ? point - of - load power solutions ? telecommunications ? single - rail/single - phase supplies for processors, asics, dsp?s, etc. ordering information sales code description package zspm1025ca1w 0 zspm1025c lead - free qfn24 ? temperature range: - 40c to +125c 7? reel zspm1025da1w 0 zspm1025d lead - free qfn24 ? temperature range: - 40c to +125c 7? reel zspm8725 - kit evaluation kit for zspm1025c with pmbus? communication interface * kit zspm8825 - kit evaluation kit for zspm1025d with pmbus? communication interface * kit * pink power designer? gui for kit can be downloaded from the idt web site at www.idt.com/zspm1025 c or www.idt.com/zspm1025 d . corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole d iscretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt' s products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, a bsent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered tradem arks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved. sequencer configurable error handler clock generation ov detection oc detection flash adc cpu core nvm ( otp ) 1 . 8 v reg digital 1 . 8 v reg analog vref vfbp vfbn v d d 5 0 avdd 18 vdd 18 adaptive digital controller pwm lse pwm vfb digital control loop isnsp isnsn current sensing hkadc int . temp sense temp bias current source vrefp 3 . 3 v reg a d c v r e f gpio g p i o 0 p g o o d c o n t r o l g p i o 1 g p i o 2 g p i o 3 dac dac average current sensing ot detection vin ov / uv detection config 0 config 1 vin vdd 33 vout uv detection zspm10 25c/d block diagram
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 3 january 22, 2016 contents features ................................................................................................................................................................... 1 benefits .................................................................................................................................................................... 1 list of figures .......................................................................................................................................................... 4 list of tables ........................................................................................................................................................... 5 1 ic characteristics ............................................................................................................................................. 6 1.1. absolute maximum ratings ....................................................................................................................... 6 1.2. recommended operating conditions ....................................................................................................... 7 1.3. electrical parameters ................................................................................................................................ 7 2 product summary ........................................................................................................................................... 10 2.1. overview .................................................................................................................................................. 10 2.2. pin descr iption ......................................................................................................................................... 12 2.3. available packages ................................................................................................................................. 13 3 functional description .................................................................................................................................... 13 3.1. power supply circuitry, reference decoupling, and grounding ............................................................ 13 3.2. reset/start - up behavior .......................................................................................................................... 14 3.3. digital power control ............................................................................................................................... 14 3.3.1. overview ........................................................................................................................................... 14 3.3.2. outpu t voltage feedback ................................................................................................................. 14 3.3.3. digital compensator ......................................................................................................................... 14 3.3.4. power sequencing and the control pin ...................................................................................... 15 3.3.5. pre - biased start - up and soft - off ...................................................................................................... 17 3.3.6. current sensing ................................................................................................................................ 17 3.3.7. temperature measurement .............................................................................................................. 18 3.4. fault monitoring and response generation ............................................................................................ 18 3.4.1. output over/under voltage .............................................................................................................. 18 3.4.2. output current protection ................................................................................................................. 19 3.4.3. over - temperature protection ........................................................................................................... 19 3.5. monitoring and debugging via i 2 c ? ....................................................................................................... 19 4 application information ................................................................................................................................... 20 4.1. typical application circuit ....................................................................................................................... 20 4.2. pin strap options of the zspm1025c/d ................................................................................................. 23 4.2.1. config0 ? output voltage .............................................................................................................. 23 4.2.2. config1 ? compensation loop and output voltage slew rate .................................................... 24 4.3. typical performance measurements for the zspm1025c and zspm1025d ......................................... 27 4.3.1. typical load transient response ? zspm1025c ? capacitor range #1 ? comp0 ........................ 28 4.3.2. typical load transient response ? zspm1025c ? capacitor range #2 ? comp1 ........................ 29 4.3.3. typical load transient response ? zspm1025c ? capacitor range #3 ? comp2 ........................ 30 4.3.4. typical load transient response ? zspm1025c ? capacitor range #4 ? comp3 ........................ 31
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 4 january 22, 2016 4.3.5. typical load transient response ? zspm1025d ? capacitor range #1 ? comp0 ........................ 32 4.3.6. typical load transient response ? zspm1025d ? capacitor range #2 ? comp1 ........................ 33 4.3.7. typical load transient response ? zspm1025d ? capacitor range #3 ? comp2 ........................ 34 4.3.8. typical load transient response ? zspm1025d ? capacitor range #4 ? comp3 ........................ 35 5 mechanical specifications .............................................................................................................................. 36 6 glossary ......................................................................................................................................................... 37 7 ordering information ...................................................................................................................................... 37 8 related documents ........................................................................................................................................ 38 9 document revision history ............................................................................................................................ 38 list of figures figure 2.1 typical application circuit with a 5 v supply voltage ...................................................................... 10 figure 2.2 block diagram ................................................................................................................................... 11 figu re 2.3 pin - out qfn24 package .................................................................................................................. 13 figure 3.1 simplified block diagram for the digital compensation ................................................................... 15 figure 3.2 power sequencing ............................................................................................................................ 16 figure 3.3 inductor current sensing using the dcr method ............................................................................ 17 figure 4.1 zspm1025c ? application circuit with a 5v supply voltage ........................................................... 20 figure 4.2 zspm1025d ? application circuit with a 5v supply voltage ........................................................... 21 figure 4 - 3 5 to 15a load step ? min. capacitance ........................................................................................... 28 figure 4 - 4 15 to 5a load step ? min. capacitance ........................................................................................... 28 figure 4 - 5 5 to 15a load step ? max. capacitance .......................................................................................... 28 figure 4 - 6 15 to 5a load step ? max. capacitance .......................................................................................... 28 figure 4 - 7 open loop bode plots ...................................................................................................................... 28 figure 4 - 8 5 to 15a load step ? min. capacitance ........................................................................................... 29 figure 4 - 9 15 to 5a load step ? min. capacitance ........................................................................................... 29 figure 4 - 10 5 to 15a load step ? max. capacitance .......................................................................................... 29 figure 4 - 11 15 to 5a load step ? max. capacitance .......................................................................................... 29 figure 4 - 1 2 open loop bode plots ...................................................................................................................... 29 figure 4 - 13 5 to 15a load step ? min. capacitance ........................................................................................... 30 figure 4 - 14 15 to 5a load step ? min. capacitance ........................................................................................... 30 figure 4 - 15 5 to 15a load step ? max. capacitance .......................................................................................... 30 figure 4 - 16 15 to 5a load step ? max. capacitance .......................................................................................... 30 figure 4 - 17 open loop bode plots ...................................................................................................................... 30 figure 4 - 18 5 to 15a load step ? min. capacitance ........................................................................................... 31 figure 4 - 19 15 to 5a load step ? min. capacitance ........................................................................................... 31 figure 4 - 20 5 to 15a load step ? max. capacitance .......................................................................................... 31 figure 4 - 21 15 to 5a load step ? max. capacitance .......................................................................................... 31 figure 4 - 22 open loop bode plots ...................................................................................................................... 31
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 5 january 22, 2016 figure 4 - 23 5 to 20a load step ? min. capacitance ........................................................................................... 32 figure 4 - 24 20 to 5a load step ? min. capacitance ........................................................................................... 32 figure 4 - 25 5 to 20a load step ? max. capacitance .......................................................................................... 32 figu re 4 - 26 20 to 5a load step ? max. capacitance .......................................................................................... 32 figure 4 - 27 open loop bode plots ...................................................................................................................... 32 figure 4 - 28 5 to 20a load step ? min. capacitance ........................................................................................... 33 figure 4 - 29 20 to 5a load step ? min. capacitance ........................................................................................... 33 figure 4 - 30 5 to 20a load step ? max. capacitance .......................................................................................... 33 figure 4 - 31 20 to 5a load step ? max. capacitance .......................................................................................... 33 figure 4 - 32 open loop bode plots ...................................................................................................................... 33 figure 4 - 33 5 to 20a load step ? min. c apacitance ........................................................................................... 34 figure 4 - 34 20 to 5a load step ? min. capacitance ........................................................................................... 34 figure 4 - 35 5 to 20a load step ? max. capacitance .......................................................................................... 34 figure 4 - 36 20 to 5a load step ? max. capacitance .......................................................................................... 34 figure 4 - 37 open loop bode plots ...................................................................................................................... 34 figure 4 - 38 5 to 20a load step ? min. capacitance ........................................................................................... 35 figure 4 - 39 20 to 5a load step ? min. capacitance ........................................................................................... 35 figure 4 - 40 5 to 20a load step ? max. capacitance .......................................................................................... 35 figure 4 - 41 20 to 5a load step ? max. capacitance .......................................................................................... 35 figure 4 - 42 open loop bode plots ...................................................................................................................... 35 figure 5.1 24- pin qfn package drawing .......................................................................................................... 36 list of tables table 3.1 power sequencing timing ................................................................................................................ 16 table 3.2 power good (pgood) output thresholds ...................................................................................... 16 table 3.3 fault configuration overview ........................................................................................................... 18 table 4.1 passive component values for the application circuits .................................................................. 22 table 4.2 pin strap resistor values ................................................................................................................. 23 table 4.3 zspm1025c and zspm1025d - nominal vout pin - s trap resistor selection (config0 pin) ..... 24 table 4.4 recommended output capacitor ranges ........................................................................................ 25 table 4.5 zspm1025c and zspm1025d - compensator and vout slew rate pin strap resistor selection ........................................................................................................................................... 26
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 6 january 22, 2016 1 ic c haracteristics note: the absolute maximum ratings are stress ratings only. the zspm10 2 5 c/d might not function or be operable above the recommended operating conditions. stresses exceeding the absolute maximum ratings might also damage the device. in addition, extended exposure to stresses above the recommended operating conditions might affect device reliability. idt does not recommend designing to the ?absolute maximum ratings.? 1.1. absolute maximum ratings parameter pins conditions min typ max units supply voltages 5 v supply voltage vdd50 dv/dt < 0.15v/ s - 0.3 5.5 v max imum slew rate 0.15 v/ s 3.3 v supply voltage vdd33 - 0.3 3.6 v 1.8 v supply voltage vdd18 avdd18 - 0.3 2.0 v digital pins digital i/o pins gpio x control pgood lse pwm - 0.3 5.5 v analog pins current sensing isnsp isnsn - 0.3 5.5 v voltage feedback vfbp vfbn - 0.3 2.0 v all other analog pin s adc v ref vrefp temp vin configx - 0.3 2.0 v ambient conditions s torage temperature -40 150 c electrostatic d ischarge ? human body model 1) +/ -2k v electrostatic d ischarge ? charge device model 1) +/ - 500 v 1) esd testing is performed according to the respective jesd22 jedec standard.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 7 january 22, 2016 1.2. recommended operating conditions parameter symbol conditions min typ max units ambient conditions operation temperature t amb -40 125 c thermal resistance junction to ambient ja 40 k/w 1.3. electrical parameters parameter symbol conditions min typ max units supply voltages 5 v supply voltage ? vdd50 pin v vdd50 4. 7 5 5 .0 5. 2 5 v 5 v supply current i vdd50 vdd50 =5.0 v 23 ma 3.3 v supply voltage v vdd33 supply for both the vdd33 and vdd50 pins if the internal 3.3v regulator is not used. 3.0 3.3 3.6 v 3.3 v supply current i vdd33 vdd50 = vdd33 =3.3 v 23 ma internally generated supply voltages 3.3 v supply volta ge ? vdd33 pin v vdd33 vdd50 =5.0 v 3.0 3.3 3.6 v 3.3 v output current i vdd33 vdd50 =5.0 v 2.0 ma 1.8 v supply voltages ? avdd18 and vdd18 pins v avdd18 v vdd18 vdd50 =5.0 v 1.72 1.80 1.98 v 1.8 v output current 0 ma power - on reset threshold for vdd33 pin ? on v th_por_on 2 . 8 v power - on reset threshold for vdd33 pin ? off v th_por_off 2. 6 v digital io pins (gpio x , control, pgood) input high voltage vdd33 =3.3 v 2.0 v input low voltage vdd33 =3.3 v 0.8 v output high voltage vdd33 =3.3 v 2.4 vdd33 v output low voltage 0. 5 v input leakage current 1 a output current - high 2.0 ma output current - low 2.0 ma
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 8 january 22, 2016 parameter symbol conditions min typ max units digital io pins with tri - state capability (lse, pwm) output high voltage vdd33=3.3 v 2.4 vdd33 v output low voltage 0.5 v output current - high 2.0 ma output current - low 2.0 ma tri - state leakage current 1.0 a output voltage (without external feedback divider ; see section 3.3.2 ) set - point voltage 0 1.4 v set - point resolution 1.4 mv set - point accuracy vout=1. 2 v 1 % inductor current measurement common mode voltage - isnsp and isnsn pins to agnd 0 5.0 v differential voltage range across isnsp and isnsn pins 100 mv accuracy 10 % digital pulse width modulator switching frequency f sw 500 khz resolution 163 ps frequency accuracy 2.0 % duty cycle 2.5 100 % over - voltage protection reference dac set - point voltage 0 1.58 v resolution 25 mv set point accuracy 2 % comparator hysteresis 35 mv housekeeping analog -to - digital converter (hkadc) input pins input voltage ? temp, vin, config0, and config1 pins 0 1.44 v source impedance vin sensing 3 k ? adc resolution 0.7 mv external temperature measurement (note: only pn - junction sense elements are supported)
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 9 january 22, 2016 parameter symbol conditions min typ max units bias currents for external temperature sensing ? temp pin 60 a resolution ? temp pin 0. 16 k accuracy of measurement ? temp pin 5.0 k internal temperature measurement resolution 0.22 k accuracy of measurement 5.0 k
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 10 january 22, 2016 2 product summary 2.1. overview the zspm1025c and zspm1025d are true - digital single - phase pwm controllers optimally configured for use with the murata power solutions 25a power block oklp - x/25 in smart digital power solutions. the zspm1025c/d has a digital power control loop incorporating output voltage sensing, averag e inductor current sensing , and extensive fault monitoring and handling features . s everal different functional units are integrated in the device . a dedicated digital control loop is used to provide fast loop response and optimal output voltage regulation. this includes output voltage sensing, average inductor current sensing, a digital control law , and a digital pulse - width modulator (dpwm). in parallel, a dedicated error handler allows fast and flexible detection of error sign als and their appropriate han dling . a housekeeping analog - to - digital converter (hkadc) ensures the reliable and efficient measurement of environmental signals , such as input voltage and temperature. an application - specific, low - energy integrated microcontroller is use d to control the overall system. i t manages configuration of the various logic unit s according to the preprogrammed configuration look - up tables and the external configuration resistors connected to the config0 and config1 pins . these pin - strapping resistors expedite conf iguration of output voltage, compensation , and rise time without requiring digital communication. idt ?s pink power designer? graphical user interface (gui) allows the user to monitor the controller?s measurements of the environmental signals and the status of the error handler via the gpio2 and gpio3 pins. figure 2 . 1 typical application circuit with a 5 v supply voltage gpio 2 gpio 1 gpio 0 config 1 config 0 agnd adcvref vrefp avdd 18 vdd 18 vdd 50 vdd 33 gnd vin temp pwm lse isnsp isnsn vfbp vfbn + 5 v + vout pgnd vin c 1 , c 2 , c 3 c 4 , c 5 , c 6 r 1 r 2 , r 3 r 4 c 8 r 7 r 8 r 5 r 6 c 7 zspm 1025 c / d murata oklp - x / 25 - w 12 - c vin + 5 v + 5 v gnd pwm temp vout + cs - cs gnd enable cin cout control pgood gpio 3
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 11 january 22, 2016 a high - reliability, high - temperature one - time programmable memory (otp) is used to store configuration param - eters. all required bias and reference voltages are internally derived from the external supply voltage. figure 2 . 2 block d iagram sequencer configurable error handler clock generation ov detection oc detection flash adc cpu core nvm ( otp ) 1 . 8 v reg digital 1 . 8 v reg analog vref vfbp vfbn v d d 5 0 avdd 18 vdd 18 adaptive digital controller pwm lse pwm vfb digital control loop isnsp isnsn current sensing hkadc int . temp sense temp bias current source vrefp 3 . 3 v reg a d c v r e f gpio g p i o 0 p g o o d c o n t r o l g p i o 1 g p i o 2 g p i o 3 dac dac average current sensing ot detection vin ov / uv detection config 0 config 1 vin vdd 33 vout uv detection
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 12 january 22, 2016 2.2. pin descriptio n pin name direction type description 1 agnd input supply analog ground 2 vrefp output supply reference terminal 3 vfbp input analog positive input of d ifferential feedback voltage sensing 4 vfbn input analog negative input of d ifferential feedback voltage sensing 5 isnsp input analog positive input of d ifferential current sensing 6 isnsn input analog negative input of d ifferential current sensing 7 temp input analog connection to e xternal temperature sensing element 8 vin input analog power supply input voltage sensing 9 config0 input analog configuration s election 0 10 config1 input analog configuration s election 1 11 pwm output digital h igh - s ide fet c ontrol s ignal 12 lse output digital low - s ide fet control s ignal 13 pgood output digital pgood output (i nternal pull - down) 14 control input digital control input ? active high 15 gpio 0 input /output digital general purpose input/output pin 16 gpio1 input/output digital general purpose input/output pin 17 gpio2 input/output digital general purpose input/output pin 18 gpio3 input/output digital general purpose input/output pin 19 gnd input supply digital ground 20 vdd18 output supply internal 1.8 v digital supply terminal 21 vdd33 input/output supply 3.3 v supply voltage terminal 22 vdd50 input supply 5.0 v supply voltage terminal 23 avdd18 output supply internal 1.8 v analog supply terminal 24 adcvref input analog analog - to - digital converter (adc) reference terminal pad pad input analog exposed p ad , digital ground
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 13 january 22, 2016 2.3. available packages the zspm10 25c/d is available in a 24- pin qfn package. the pin - out is shown in figure 2 . 3 . the mech a nical drawing of the package can be found in figure 5 . 1 . figure 2 . 3 pin -o ut qfn24 p ackage 3 functional description 3.1. power s upply c ircuitry , r eference d ecoupling , and g rounding the zspm10 25c/d incorporate s several internal power regulators in order to derive all required supply and bias v oltage s from a single external supply v oltage . this supply v oltage can be either 5 v or 3.3 v depending on whether the internal 3.3 v regulator shou ld be used. if the internal 3.3 v regulator is not used, 3.3 v mu st be supplied to the 3.3v and 5 v supply pin s . decoupling capacitors are required at the vdd 33, vdd18, and avdd18 pins (1.0f minimum; 4.7 f recommended). if the 5.0 v supply voltage is used, i.e. , the internal 3.3 v regulator is used, a small load current can be drawn from the vdd33 pin. t his can be used to supply pull - up resistors , for example. the reference v oltage s required for the analog - to - digital converters are generated within the zspm10 25c/d . e xternal decoupling must be provided betw een the vref p and adcvref pins . therefore, a 4 . 7 f capacitor is required at the vref p pin , and a 100 n f capacitor is required at the adcvref pin . the two pins should be connected with ap proximately 50? resistance in order to provide sufficient decoupling between the pins . three different ground connection s (the pad, agnd pin, and gnd pin) are available on the outside of the package. these should be connected together to a single ground tie. a differentiation between analog and digital ground is not required. a d c v r e f a v d d 1 8 v d d 5 0 v d d 3 3 v d d 1 8 g n d pad 19 20 21 22 24 23 isnsp isnsn vfbp vfbn agnd 4 2 1 3 5 6 vrefp p wm l s e v i n t e m p c o n f i g 0 c o n f i g 1 7 8 12 10 9 11 control pgood gpio 1 gpio 2 gpio 3 13 14 15 16 18 17 gpio 0
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 14 january 22, 2016 3.2. reset/ s tart - up b ehavior the zspm10 25c/d employs a n internal power - on- reset (por) circuit to ensure proper sta rt up and sh u t down with a changing supply voltage . o nce the supply voltage increases above the por threshold voltage (see section 1.3 ) , the zspm10 25c/d begins the internal start - up process. upon its completion , the device is ready for operation. 3.3. d igital power control 3.3.1. overview the digital power control loop consists of the integral parts required for the control functionality of the zspm10 25c/d . a high - speed analog front - end is used to digitize the output volt age. a digital control core uses the acquired information to provide d uty - cycle information to the pwm that controls the drive signals to the power stage. 3.3.2. output voltage f eedback the v oltage feedback signal is sampled wit h a high - speed analog front - end. the feedback v oltage is differential ly measured and subtracted from the voltage reference provided by a reference digital - to - analog converter (dac) using an error amplifier. a flash adc is then used to convert the v oltage into its digital equivalent. this is followed by i nternal digital filtering to improve the system?s noise rejection. 3.3.2.1. zspm1025c the zspm1025c has been designed for an output voltage range from 0.62 to 1.20v. t he vfbp pin should be connected to the converter output through a 1.75k resistor , and a small filter capacitor, typically 22pf, should be connected betwe en the vfbp and vfbn pins of the zspm1025c. 3.3.2.2. zspm1025d the zspm1025d has been designed for an output voltage range from 1.25 to 3.40v. a n external feedback divider is required for the zspm1025d . the vfbp pin should be connected to the converter output throu gh a 1.75k resistor , and a 1k resistor should be connected between the vfbp and vfbn pin of the zspm1025d. a small filter capacitor, typically 22pf, should also be connected between the vfbp and vfbn pins of the zspm1025d. 3.3.3. digital compensator the sampled output v oltage is processed by a digital control loop in order to modulate the dpwm output signal s controlling the power stage. this digital control loop works as a v oltage - mode controller using a pid - type compensation. the basic structure of the controller is shown in figure 3 . 1 . the proprietary state - law ? control (slc) concept features two parallel compensators , steady - state operation, a nd fast transient operation. the zspm10 25c/d implements fast, reliable switching between the different compensation mode s in order to ensure good transient performance and quiet steady state. this has been utilized to tun e the compensators individually for the respective needs ; i.e. quiet steady - state and fast transient performance.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 15 january 22, 2016 figure 3 . 1 simplified block d iagram for the d igital c ompensation t hree different techniques are used to improve transient performance further : ? tru - sample t echnology ? is used to acquire fast, accurate , and continuous information about the output vol - tage so that the device can react quickly to any change in output voltage. tru - sample technology? reduces phase - lag caused by sampling delays, reduces noise sensitivity , and improves transient performance. ? t h e sub - cycle response ? (scr) technique, a method to drive the dpwm asynchronous ly during load tran - sients, allows limiting the maximum deviation o f the output voltage and recharging the output capacitors faster. ? a non linear gain adjustment is used during large load transients to boost the loop gain and reduce the settling time. 3.3.4. power s equencing and the control p in the zspm10 25c/d has a set of pre - configured power - sequencing features . t he typical sequence of events is shown in figure 3 . 2 . the individual values for the delay, ramp time , and po st ramp time are listed in table 3 . 1 . note that the device is slew - rate controlled for ramping. hence, when pin - strapping options for the output voltage are used, the ramp time can change based on the configured slew - rate and the actual selected output voltage . the slew rate can be selected in the application circuit using the pin - strap options as explained in secti on 4.1 . the control pin is pre - configured for active high operation. the zspm10 25c/d features a p ower g ood (pgood) output , which can be used to ind icate the state of the power rail. if the output voltage level is above the power good on threshold , the pin is set to active, indicating a stable output voltage on the rail. the thresholds for the power good output tu rn - on and turn - off are listed in table 3 . 2 . note that the power good thresholds are stored in the device as factor s relative to the nominal output voltage. hence, using the strapping o ptions ( see section 4.1 ) to change the output voltage level also change s the pgood thresholds.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 16 january 22, 2016 figure 3 . 2 power s equencing table 3 . 1 power sequencing timing parameter zspm1025c zspm1025d t on_delay 10ms 10ms t on_rise pin strap selectable (see section 4.1 ) pin strap selectable (see section 4.1 ) t on_max 188ms 188ms t off_delay 10ms 10ms t off_fall * 50ms (vout = 1.20v) ramp down slew rate is 0.024v/ms 50ms (vout = 1.80v) ramp down slew rate is 0.036v/ms t off_max 188ms 188ms * t off_fall is implemented as a slew rate by the zspm1025c/d. use the device - specific slew rate and the selected nominal output voltage to calculate the actual t off_fall in milliseconds. table 3 . 2 power good (pgood) output thresholds parameter value on level 95% of vout n ominal vout nominal is pin - strap selectable (see section 4.1 ) off level 90% of vout nominal vout nominal is pin - strap selectable (see section 4.1 ) t t on_ delay t on_ rise t on_ max t off _ delay t off _ fall 0 v v outnom t off _ max control pin control pin v pgood _ on v pgood _ off
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 17 january 22, 2016 3.3.5. pre - biased s tart - up and so ft- off dedicated pre - biased start - up logic ensures proper start - up of the power converter when the output capacitors are pre - charged to a non - zero output voltage . closed - loop stability is ensured during this phase. when the dc/dc converter output is disabled, i.e. when the control pin is set low, the zspm1025c/d will execute the soft - off sequence. the soft - off sequence will ramp down the output voltage to 0v and se t the pwm output in a tri - state condition. 3.3.6. current s ensing the zspm10 2 5 c/d offers cycle - by - cycle average current sensing and over - current protectio n . a dedicated adc is used to provide fast and accurate current information over the switch ing period. the acquired information is compared with the pre - configured over - current threshold to trigger an over - cur rent fault event . dc r current sensing across the inductor on the murata oklp - x /25 - w12 - c is supported . additionally, the device uses dcr temperature co mpensation via the external temperature sense element. this increases the accuracy of the current sense method by counteracting the significant change of the dcr over temperature. the schematic of the required current sensing circuitry is shown in figure 3 . 3 for the widely - used dcr current - sensing method, which uses the parasitic resistance of the inductor to acquire the current information. the principle is based on a matched time - constant between the inductor and the low - pass filter built from a 2.15k resi stor mounted on the murata oklp - x/25 - w12 - c power block and c 8 . resistor r 6 should be a precision 2.15k resistor in order to provide good dc voltage rejection, .i.e. reduce the influence of the output voltage level on the current measurement. figure 3 . 3 inductor c urrent s ensing using the dcr m ethod zspm 1025 + vout 2 . 15 kohm r 6 2 . 15 kohm isnsp isnsn c 8 220 nf l dcr murata oklp - x / 25 - w 12 - c + cs - cs
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 18 january 22, 2016 t o improve the accuracy of the current measurement , which can be adversely affected by the temperature coefficient of the inductor?s dcr, the zspm10 25c/d features temperature compensation via the external temperature sensing. t he temperature of the inductor can be measured with an external temperature sense element placed close to the inductor. this information is used to adapt the gain of the current sens e path to compensate for the increase in actual dcr. 3.3.7. temperature measurement the zspm1025 c/d features two independent temper ature measurement units. t he internal temperature s ensing measures the temperature inside the ic; the external temperature sen sing e lement is placed on the murata oklp - x/25 - w12 - c power block. the zspm1025 c/d drives 60 a into the external temperature sensing element and measures the voltage on the temp pin. 3.4. fault m onitoring and r esponse g eneration the zspm10 2 5 c/d monitors various signals for possible fault conditions during operation. the fault thresholds of the zspm1025c/d controllers are given in ta ble 3 . 3 . ta ble 3 . 3 fault c onfiguration o verview signal fault t hreshold output over - voltage fault 125% of nominal vout * output under - voltage fault 75% of nominal vout * input over - voltage fault 13.80v input under - voltage fault 7.00v over - current fault 30.0a external over - temperature fault 105c internal over - temperature fault 100c * nomi nal vout is selected by the pin - strap resistor on the config0 pin. the controller fault handling will infinitely try to restart the converter on a fault condition. in analog controllers, this infinite re - try feature is also known as ?hiccup mode.? 3.4.1. output o ver / u nder voltage to prevent damage to the load, the zspm10 2 5 c/d utilizes an output over - v oltage protection circuit. t he v oltage at vfbp is continuously compared with a configurable threshold using a high - speed analog comparator. if the v oltage exceeds the configured threshold, the fault response is generated and the pw m output is set to low . t he zspm10 2 5 c/d also mo nitors the output v oltage with a lower threshold . if the output v oltage falls below the under - voltage fault level, a fault event is generat e d and the pwm output is set to low . note that the fault thresholds are stored in the zspm10 2 5 c/d as f actor s relative to the nominal output voltage. hence, using the strapping options ( see section 4.1 ) to change the output voltage level, also change s the fault thresholds.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 19 january 22, 2016 3.4.2. output c urrent p rotectio n the zspm10 2 5 c/d continuously monitors the average inductor current and utilizes this informa tion to protect the power supply against excessive output current . 3.4.3. over - t emperature p rotection the zspm10 2 5 c/d monitors internal and external temperature. for the temperature fault conditions a soft - off sequence is started. the soft - off sequence will ramp down the output voltage to 0v and set the pwm output in a tri - state condition. 3.5. monitoring and debugging via i 2 c ? the pink power designer? gui can be used to monitor the internal measurement signal s of the zspm1025c/d during the developm ent phase. the status of the internal fault handler can also be monitored within the pink power designer? gui. the pink power designer? gui communicates with the zspm10 25c/d via an i 2 c? * interface in which the scl signal is connected to the gpio 3 pin and the sda signal is connected to the gpio 2 pin . * i 2 c ? is a trademark of nxp.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 20 january 22, 2016 4 application information the zspm1025c/d controllers have been designed and pre - configured to operate with the murata oklp - x/25 - w12 - c power block, which is a complete point - of - load solution for 25a output curre nts. this section includes information about the typical application circuit s an d recommended component values. the pin - strap configuration options for the zspm1025c/d are also documented in this section . 4.1. typical application circuit schematics for the typi cal application circuits for the zspm1025c and zspm1025d respectively are shown in figure 4 . 1 and figure 4 . 2 . a list of recommended component values for the passive components can be found in table 4 . 1 . figure 4 . 1 zspm1025c ? application circuit with a 5v supply voltage gpio 2 gpio 1 gpio 0 config 1 config 0 agnd adcvref vrefp avdd 18 vdd 18 vdd 50 vdd 33 gnd vin temp pwm lse isnsp isnsn vfbp vfbn + 5 v + vout pgnd vin c 1 , c 2 , c 3 c 4 , c 5 , c 6 r 1 r 2 , r 3 c 8 r 7 r 8 r 5 r 6 c 7 zspm 1025 c murata oklp - x / 25 - w 12 - c vin + 5 v + 5 v gnd pwm temp vout + cs - cs gnd enable cin cout control pgood gpio 3 pgood on / off u 1 u 2
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 21 january 22, 2016 figure 4 . 2 zspm1025d ? application circuit with a 5v supply voltage gpio 2 gpio 1 gpio 0 config 1 config 0 agnd adcvref vrefp avdd 18 vdd 18 vdd 50 vdd 33 gnd vin temp pwm lse isnsp isnsn vfbp vfbn + 5 v + vout pgnd vin c 1 , c 2 , c 3 c 4 , c 5 , c 6 r 1 r 2 , r 3 c 8 r 7 r 8 r 5 r 6 c 7 zspm 1025 d murata oklp - x / 25 - w 12 - c vin + 5 v + 5 v gnd pwm temp vout + cs - cs gnd enable cin cout control pgood gpio 3 pgood on / off u 1 u 2 r 4
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 22 january 22, 2016 table 4 . 1 passive component values for the application circuit s reference designator component value description c1 1.0 f ceramic capacitor. c2 4.7 f ceramic capacitor. recommended 4.7 f; m inimum 1.0 f . c3 4.7 f ceramic capacitor. recommended 4.7 f; mi nimum 1.0 f . c4 4.7 f ceramic capacitor. recommended 4.7 f; m inimum 1.0 f . c5 4.7 f ceramic capacitor. recommended 4.7 f; m inimum 1.0 f . c6 100nf c7 22pf output voltage sense filtering capacitor. recommended 22pf; maximum 1 nf . c8 220nf* dcr current - sense filter capacitor. cin input filter capacitors. can be a combination of ceramic and electrolytic capacitors. cout output filter capacitors. see section 4.2.2 for more information on the output capacitor selection. r1 51* r2, r3 pin - strap configuration resistors. see sections 4.2.1 and 4.2.2 for informa tion on application - specific values. r4 1.0k * output voltag e feedback divider bottom resistor. connect between the vfbp and vfbn pins. important : r4 must not be used with the zspm1025 c . if r4 is used with the zspm1025c , the output voltage will be much higher than the nominal output voltage . r5 1.75k * output voltage feedback divider top resistor. connect between the output terminal and the vfbp pin. r6 2.15k * dcr current sense filter resistor. r7 9.1k * input voltage divider top resistor. connect between the main power input and the vin pin of the zspm1025c/d. r8 1.0k * input voltage divider bottom resistor. connect between the vi n and agnd pins of the zspm1025c/d . notes: * fixed component values that must not be changed.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 23 january 22, 2016 4.2. pin strap options of the zspm1025c/d the zspm10 25c/d provides t w o pin - strap configuration pins. the config0 pin is used to se lect the nominal output voltage of the non - isolated dc/dc converter. the config1 is used to select a set of compensation loop parameters in combin ation with the slew rate for the output voltage during the power - up sequence. there are four set s of compensation loop parameters that have been optimized for different ranges of output capacitance. the config0 and config1 pins are used to determine the index of the selected valu es using the resistor values listed in table 4 . 2 . each pin provides 30 configuration indexes based on resistor values from the e96 series . a resistor variation of ~2% is taken into account for initial tolerance and temperature dependency. the values are read during the initialization phase after a por event and are then use d to look up the selected index from the pre - configured look - up tables. based on the index read by the zspm1025c/d , the controller will load the corresponding configuration from the otp memory of the device. table 4 . 2 pin strap resistor values index resistor value using the e96 series index resistor value using the e96 series 0 0 15 5.360k 1 392 16 6.040k 2 576 17 6.810k 3 787 18 7.680k 4 1.000k 19 8.660k 5 1.240k 20 9.530k 6 1.500k 21 10.50k 7 1.780k 22 11.80k 8 2.100k 23 13.00k 9 2.430k 24 14.30k 10 2.800k 25 15.80k 11 3.240k 26 17.40k 12 3.740k 27 19.10k 13 4.220k 28 21.00k 14 4.750k 29 23.20k 4.2.1. config0 ? output voltage the nominal output voltage of th e zspm1025c/d is set with a pin - strap resistor on the config0 pin. the selectable output vol tages and the corresponding pin - strap resistor index are given in table 4 . 3 . the nominal output voltage set points given for the zspm1025c ar e valid without an output voltage feedback divider. to achieve optimal performance the low pass filter consisting of resistor r5 and c7 (see figure 4 . 1 ) should be included in the application circuit. the nominal output voltage set points given for the zspm1025d are only valid if the resistors in the output vol tage feedback divider, r4 and r5 (see figure 4 . 2 ) , have the resistances specified in table 4 . 1 .
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 24 january 22, 2016 table 4 . 3 zspm1025c a nd zspm1025d - nominal vout pin - strap resistor selection (config0 pin) index resistor value using the e96 series nominal vout ? zspm1025c nominal vout ? zspm1025d 0 0 0.62 v 1.25 v 1 392 0.64 v 1.30 v 2 576 0.66 v 1.35 v 3 787 0.68 v 1.40 v 4 1.000k 0.70v 1.45 v 5 1.240k 0.72v 1.50 v 6 1.500k 0.74v 1.55 v 7 1.780k 0.76 v 1.60 v 8 2.100k 0.78 v 1.65 v 9 2.430k 0.80 v 1.70 v 10 2.800k 0.82v 1.75 v 11 3.240k 0.84 v 1.80 v 12 3.740k 0.86v 1.85 v 13 4.220k 0.88 v 1.90 v 14 4.750k 0.90 v 1.95 v 15 5.360k 0.92 v 2.00 v 16 6.040k 0.94 v 2.10 v 17 6.810k 0.96 v 2.20 v 18 7.680k 0.98 v 2.30 v 19 8.660k 1.00 v 2.40 v 20 9.530k 1.02 v 2.50 v 21 10.50k 1.04 v 2.60 v 22 11.80k 1.06 v 2.70 v 23 13.00k 1.08 v 2.80 v 24 14.30k 1.10 v 2.90 v 25 15.80k 1.12 v 3.00 v 26 17.40k 1.14v 3.10 v 27 19.10k 1.16v 3.20 v 28 21.00k 1.18 v 3.30 v 29 23.20k 1.20 v 3.40 v 4.2.2. config1 ? compensation loop and output voltage slew rate the zspm1025c/d controllers can be configured to operate over a wide range of output capacitance. four ranges of output capacitance have been specified to match typical customer requirements (see table 4 . 4 ). typical performance measurements for both load transient performance and open - loop bode plots can be found in section 4.3 . using less output capacitance than the minimum capacitance given in table 4 . 4 is not recommended.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 25 january 22, 2016 table 4 . 4 recommended output capacitor ranges capacitor range ceramic capacitor bulk electrolytic capacitors #1 minimum 200 f maximum 400 f none #2 minimum 400 f maximum 1000 f none #3 minimum 100 f maximum 600 f minimum 2 x 470 f, 7m esr maximum 5 x 470 f, 7m esr #4 minimum 400 f maximum 1000 f minimum 4 x 470 f, 7m esr maximum 10 x 470 f, 7m esr to get the optimal performance for a give n output capacitor range, one of four set s of compensation loop parameters, comp0 to comp3, should be selected with a resistor between config1 and gnd. the compensation loop parameters have been configured to ensure optimal transient performance and good control loop stability margins . for each se t of compensation loop parameters , there is a choice of seven slew rates for the output voltage during power - up. the selection of the slew rate can be used to limit the input current of the dc/dc converter while it is ramping up the output voltage. the cur rent needed to charge the output capacitors increases in direct proportion to the slew rate . table 4 . 5 gives a complete list of the selectable compensation loop parameters and slew rates together with the equivalent pin - strap resistor values.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 26 january 22, 2016 table 4 . 5 zspm1025c and zspm1025d - compensator and vout slew rate pin strap resistor selection index resistor value using the e96 series compensator vout slew rate 0 0 comp0 (capacitor range #1) 0.10 v/ms 1 392 0.20 v/ms 2 576 0.50 v/ms 3 787 1.00 v/ms 4 1.000k 2.00 v/ms 5 1.240k 5.00 v/ms 6 1.500k 10.00 v/ms 7 1.780k comp1 (capacitor range #2) 0.10 v/ms 8 2.100k 0.20 v/ms 9 2.430k 0.50 v/ms 10 2.800k 1.00 v/ms 11 3.240k 2.00 v/ms 12 3.740k 5.00 v/ms 13 4.220k 10.00 v/ms 14 4.750k comp2 (capacitor range #3) 0.10 v/ms 15 5.360k 0.20 v/ms 16 6.040k 0.50 v/ms 17 6.810k 1.00 v/ms 18 7.680k 2.00 v/ms 19 8.660k 5.00 v/ms 20 9.530k 10.00 v/ms 21 10.50k comp3 (capacitor range #4) 0.10 v/ms 22 11.80k 0.20 v/ms 23 13.00k 0.50 v/ms 24 14.30k 1.00 v/ms 25 15.80k 2.00 v/ms 26 17.40k 5.00 v/ms 27 19.10k 10.00 v/ms 28 21.00k comp0 0.10 v/ms 29 23.20k 0. 1 0 v/ms
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 27 january 22, 2016 4.3. typical performance measurements for the zspm1025 c and zspm1025d the pre - programmed compensation l oop parame ters for the zspm1025c and zspm 1025d have been designed to ensure stability and optimal tran sient performance for the oklp - x /25 - w12 - c power block from murata in combination with one of the four output capacitor ra nges (see table 4 . 4 ) . load transient pe rformance measurements and open - loop bode plots for the zspm1025c can be found in sections 4.3 .1 to 4.3.4 . the transient load steps have been generated with a load resistor and a power mosfet located on the same circuit board as the zspm1025c and the murata oklp - x/25 - w12 - c power block. the zspm87 25- kit evaluation kit can be used to further evaluate the perfo r mance of the zspm1025c for the four output capacitor ranges. load transient pe rformance measurements and open - loop bode plots for the zspm1025d are shown in sections 4.3.5 to 4.3.8 . the transient load steps have been generated with a load resistor and a power mosfet located on the same circuit board as the zspm1025d and the murata oklp - x/25 - w12 - c power block. the zspm8825 - kit evaluation kit can be used to further evaluate the performance of the zspm1025d for the four output capacitor ranges.
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 28 january 22, 2016 4.3.1. typical load transient response ? zspm1025c ? c apacit or range #1 ? comp0 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 2 x 100 f/6.3v x5r maximum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r figure 4 - 3 5 to 15a load step ? min. capacitance figure 4 - 4 15 to 5a load step ? min. capacitance figure 4 - 5 5 to 15a load step ? max. capacitance figure 4 - 6 15 to 5a load step ? max. capacitance figure 4 - 7 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (bl ue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 100mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 29 january 22, 2016 4.3.2. typical load transient response ? zspm1025c ? c apacitor range #2 ? comp1 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r figure 4 - 8 5 to 15a load step ? min. capacitance figure 4 - 9 15 to 5a load step ? min. capacitance figure 4 - 10 5 to 15a load step ? max. capacitance figure 4 - 11 15 to 5a load step ? m ax . capacitance figure 4 - 12 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc ti me scale: 8 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 30 january 22, 2016 4.3.3. typical load transient response ? zspm1025c ? c apacitor range #3 ? comp2 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 1 x 100 f/6.3v x5r + 2 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 6 x 100 f/6.3v x5r + 5 x 470 f/6.3v/7m alumi n um electrolytic capacitor figure 4 - 13 5 to 15a load step ? mi n. capacitance figure 4 - 14 15 to 5a load step ? min. capacitance figure 4 - 15 5 to 15a load step ? max. capacitance figure 4 - 16 15 to 5a load step ? max. capacitance figure 4 - 17 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 31 january 22, 2016 4.3.4. typical load transient response ? zspm1025c ? capacitor range # 4 ? comp3 test conditions: v in = 12.0v, v out = 1.20v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r + 4 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r + 10 x 470 f/6.3v/7m aluminum electrolytic capacitor figure 4 - 18 5 to 15a load step ? min. capacitance figur e 4 - 19 15 to 5a load step ? min. capacitance figure 4 - 20 5 to 15a load step ? max. capacitance figure 4 - 21 15 to 5a load step ? max. capacitance figure 4 - 22 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 32 january 22, 2016 4.3.5. typical load transient response ? zspm1025d ? c apacitor range #1 ? comp0 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 2 x 100 f/6.3v x5r maximum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r figure 4 - 23 5 to 20a load step ? min. capacitance figure 4 - 24 20 to 5a load step ? min. capacitance figure 4 - 25 5 to 20a load step ? max. capacitance figure 4 - 26 20 to 5a load step ? max. capacitance figure 4 - 27 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue ): vout 10 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 33 january 22, 2016 4.3.6. typical load transient response ? zspm1025d ? c apacitor range #2 ? comp1 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r figure 4 - 28 5 to 20a load step ? min. capacitance figure 4 - 29 20 to 5a load step ? min. capacitance figure 4 - 30 5 to 20a load step ? max. capacitance figure 4 - 31 20 to 5a load step ? max. capacitance figure 4 - 32 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 5 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div ch1 (blue): vout 50mv/div a c ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 8 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 34 january 22, 2016 4.3.7. typical load transient response ? zspm1025d ? c apacitor range #3 ? comp2 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 1 x 100 f/6.3v x5r + 2 x 470 f/6.3v/7m alumin um electrolytic capacitor maximum output capacitance: 6 x 100 f/6.3v x5r + 5 x 470 f/6.3v/7m aluminum electrolytic capacitor figure 4 - 33 5 to 20a load step ? min. capacitance figure 4 - 34 20 to 5a load step ? min. capacitance figure 4 - 35 5 to 20a load step ? max. capacitance figure 4 - 36 20 to 5a load step ? max. capacitance figure 4 - 37 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 50mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 35 january 22, 2016 4.3.8. typical load transient response ? zspm1025d ? c apacitor range #4 ? comp3 test conditions: v in = 12.0v, v out = 1.80v minimum output capacitance: 3 x 100 f/6.3v x5r + 2 x 47 f/10v x7r + 4 x 470 f/6.3v/7m aluminum electrolytic capacitor maximum output capacitance: 7 x 100 f/6.3v x5r + 4 x 47 f/10v x7r + 10 x 470 f/6.3v/7m alumi n um electrolytic capacitor figure 4 - 38 5 to 20a load step ? min. capacitance figure 4 - 39 20 to 5a load step ? min. capacitance figure 4 - 40 5 to 20a load step ? max. capacitance figure 4 - 41 20 to 5a load step ? max. capacitance figure 4 - 42 open loop bode plots -180 -150 -120 -90 -60 -30 0 -40 -30 -20 -10 0 10 20 30 40 1 10 100 phase [degrees] gain [db] frequency [khz] max caps - gain min caps - gain max caps - phase min caps - phase ch1 (blue): vout 2 0mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ) : load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div ch1 (blue): vout 20mv/div ac ch2 (cyan ): pwm 5v/div dc ch3: ( violet ): load trigger 5v/div dc time scale: 20 s/div
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 36 january 22, 2016 5 mechanical specifications based on jedec mo - 220. all dimensions are in m illimeters. figure 5 . 1 24- pin qfn package drawing dimension m in (mm) m ax (mm) a 0.8 0.90 a 1 0.00 0.05 b 0.18 0.30 e 0.5 nom inal h d 3.90 4.1 h e 3.90 4.1 l 0.35 0.45
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 37 january 22, 2016 6 glossary term description dpwm digital pulse - width modulator dcr dc resistance fet field - effect transistor fpga field - programmable gate array gpio general purpose input/output gui graphical user interface hkadc housekeeping analog -to - digital converter ot over - temperature otp one - time programmable memory ov over - voltage pid proportional/integral/derivative por power - on - reset scr sub - cycle response? slc state - law control? spm smart power management 7 ordering inf ormation sales code description package zspm1025ca1w 0 zspm1025c lead - free qfn24 ? temperature range: - 40c to +125c 7? reel zspm1025da1w 0 zspm1025d lead - free qfn24 ? temperature range: - 40c to +125c 7? reel zspm8725 - kit evaluation kit for zspm1025c with pmbus? communication interface * kit zspm8825 - kit evaluation kit for zspm1025d with pmbus? communication interface * kit * pink power designer? gui for kit can be downloaded from the idt web site at www.idt.com/zspm1025 c or www.idt.com/zspm1025 d .
zspm1025c / zspm1025d ? 2016 integrated device technology, inc. 38 january 22, 2016 8 related documents document zspm1025c/d feature sheet zspm1025 and zspm1035 family feature sheet zspm8725 kit description (for zspm1025c only ) zspm8 8 25 kit description (for zspm1025 d only ) zspm1025c/d pink power designer? gui guide visit the following product page s on idt ?s website or contact your nearest sales office for the latest version of these documents. product pages: www.idt.com/zspm1025 c www.idt.com/zspm1025 d 9 document revision history revision date description 1.00 october 2 8 , 2013 first release. 1.01 october 15 , 2014 update for cover/header imagery and contacts. update for kit contents. update for related documents in section 8 . january 2 2 , 2016 changed to idt branding. corporate headquarters 6024 silver creek valley road san jose, ca 95138 www.idt.com sales 1- 800- 345- 7015 or 408 - 284- 8200 fax: 408 - 284- 2775 www.idt.com/go/sales tech support www.idt.com/go/support disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or specifications described herein at any time, without notice, at idt's sole d iscretion. performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, includin g, but not limited to, the suitability of idt' s products for any particular purpose, an implied warranty of merchantability, or non - infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey an y license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, a bsent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered tradem arks of idt and its subsidiaries in the united states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . all contents of this document are copyright of integrated device technology, inc. all rights reserved.

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